Pull-up resistor circuit is widely used in integrated circuits (IC), especially in the input/output (I/O) circuits. Many I/O ports typically need to be set to a default high level voltage, so that when there is no input signal, an I/O port is pulled up to the high voltage level by a pull-up resistor.
FIG. 1 shows a traditional pull-up resistor circuit of an IC circuit. As shown in FIG. 1, the pull-up resistor circuit includes a voltage source VDD, a voltage output OUT, and a PMOS transistor MP0. The source and the substrate of the PMOS transistor MP0 are connected to the voltage source VDD. The drain of the PMOS transistor MP0 is connected to voltage output OUT. The control signal RE is inputted through the gate of the PMOS transistor MP0. The voltage source VDD is connected to the power supply, and the voltage output OUT is connected to an I/O port of the IC circuit.
Under a normal mode, where a voltage of the voltage source VDD is higher than that of the voltage output OUT, when the control signal RE is low, the PMOS transistor MP0 is turned on and the resistor is enabled, therefore, the voltage on the voltage output OUT is pulled up to the same voltage level as the voltage source VDD and have the same voltage level. When the control signal RE is high, the PMOS transistor MP0 is turned off and the resistor pull-up is disabled.
However, under a high-voltage-tolerant mode, where the voltage of the voltage output OUT is higher than that of the voltage source VDD (for example, when the voltage source VDD is at 3.3V, while the voltage on the bus is 5V and the voltage output OUT is connected to the bus), even though the control signal RE is high, the PMOS transistor MP0 is still turned on. Thus, the current flows from the voltage output OUT to the voltage source VDD.
The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.